Re: [Iverilog-devel] Time in VHDL

[Stephen W. <st...@ic...>]

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That shares the literal bits that are the time value, but it
does not account for the semantics of time. If it did, it would
scale time values to local units as they cross module boundaries.
That is the crux of the problem that Orson is facing.

On 06/05/2015 12:24 PM, Martin Whitaker wrote:
> Stephen Williams wrote:
>> You are pointing out a problem with VERILOG and not VHDL vs.
>> Verilog. In Verilog, time values do not cross module boundaries
>> through ports. Doing so will get you the headaches that you see.
>> Fixing it will involve extending the verilog language.
>> 
> The SystemVerilog committee has already done this for you. See
> section 23.3.3 of 1800-2012:
> 
> "Values of all data types on variables and nets can be passed
> through ports. This is accomplished by allowing both sides of a
> port connection to have assignment-compatible data types and by
> allowing continuous assignments to variables."
> 
> So it is now legal to declare:
> 
> module m(input time t);
> 
> You can also declare:
> 
> module m(ref time t);
> 
> which lets you share a common variable.
> 
> Martin
> 
> ------------------------------------------------------------------------------
>
> 
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