Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> You are pointing out a problem with VERILOG and not VHDL vs. Verilog.
> In Verilog, time values do not cross module boundaries through ports.
> Doing so will get you the headaches that you see. Fixing it will
> involve extending the verilog language.
>
The SystemVerilog committee has already done this for you. See section 23.3.3 
of 1800-2012:

"Values of all data types on variables and nets can be passed through ports. 
This is accomplished by allowing both sides of a port connection to have 
assignment-compatible data types and by allowing continuous assignments to 
variables."

So it is now legal to declare:

   module m(input time t);

You can also declare:

   module m(ref time t);

which lets you share a common variable.

Martin