Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> Define a command line flag for VHDL compilation that sets the default
> VHDL precision. Let Verilog/SystemVerilog get its precision by its
> own means. The vhdlpp generated modules all have the default  VHDL
> time precision, and enforces this by timeprecision and timeunits
> module items. These are supposed to override Verilog `time* directives
> within the scope of the module at hand.
>
> The Verilog semantics for precision are that the elaborator finds
> the highest precision needed and uses that as the global precision.
> All time literals are scaled from units to precision by the compiler.
>
> These semantics should just work. I'm still not understanding what
> the problem is.
>
I was allowing for the case that a user might choose to translate VHDL files 
in advance, then choose a time precision at the time they compiled and 
elaborated the translated files. Your solution requires them to have chosen 
the (same) time precision when the VHDL files are translated. But maybe I'm 
allowing for something that won't get used in practice.

Martin