Re: [Iverilog-devel] Time in VHDL

[Stephen W. <st...@ic...>]

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How 'bout this...

Define a command line flag for VHDL compilation that sets the default
VHDL precision. Let Verilog/SystemVerilog get its precision by its
own means. The vhdlpp generated modules all have the default  VHDL
time precision, and enforces this by timeprecision and timeunits
module items. These are supposed to override Verilog `time* directives
within the scope of the module at hand.

The Verilog semantics for precision are that the elaborator finds
the highest precision needed and uses that as the global precision.
All time literals are scaled from units to precision by the compiler.

These semantics should just work. I'm still not understanding what
the problem is.

On 06/01/2015 12:11 PM, Martin Whitaker wrote:
> Cary R. wrote:
>> I have not looked at your pull request, but from what I am
>> reading you may have added code that addresses one of our older
>> feature requests on SourceForge so please look at them. I think
>> `resetall may be a bit heavy handed since it will change the
>> timescale, etc. that future modules/files will see. It seems like
>> the more localized SV additions would be best for setting the
>> scale and precision for only the translated modules.
> 
> Well, if future files depend on what's gone before, they're
> fundamentally broken, as nothing guarantees the order in which
> files are read.
> 
> But to summarise what I wrote yesterday:
> 
> - VHDL has a global time resolution that applies to the entire 
> elaborated design - by default this is 1fs - the VHDL standard
> allows for the user to override the default - all simulators I've
> looked at support this via a configuration file or command line
> option
> 
> I think we need to do the same.
> 
> If people don't like `resetall, then I propose the following
> alternative:
> 
> - as an Icarus extension, allow the special value 'vhdl' to be used
> in SV timeunit and timeprecision declarations - set the default
> units and precision for vhdl to 1fs - allow the +timescale option
> to override these defaults
> 
> We could use 'default' rather than 'vhdl' and use the existing
> default timescale values, but then I'd want to change the initial
> defaults.
> 
> Martin
> 
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>
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Steve Williams                "The woods are lovely, dark and deep.
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