Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Cary R. wrote:
> I have not looked at your pull request, but from what I am reading you may
> have added code that addresses one of our older feature requests on
> SourceForge so please look at them. I think `resetall may be a bit heavy
> handed since it will change the timescale, etc. that future modules/files
> will see. It seems like the more localized SV additions would be best for
> setting the scale and precision for only the translated modules.

Well, if future files depend on what's gone before, they're fundamentally 
broken, as nothing guarantees the order in which files are read.

But to summarise what I wrote yesterday:

   - VHDL has a global time resolution that applies to the entire
     elaborated design
   - by default this is 1fs
   - the VHDL standard allows for the user to override the default
   - all simulators I've looked at support this via a configuration
     file or command line option

I think we need to do the same.

If people don't like `resetall, then I propose the following alternative:

   - as an Icarus extension, allow the special value 'vhdl' to be
     used in SV timeunit and timeprecision declarations
   - set the default units and precision for vhdl to 1fs
   - allow the +timescale option to override these defaults

We could use 'default' rather than 'vhdl' and use the existing default 
timescale values, but then I'd want to change the initial defaults.

Martin