Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Maciej Sumiński wrote:
> I could not find it described explicitly in the standard, but there are
> fragments that make me think that time is just a real number that stores
> count of time units, rounded to requested precision:
> - table 21-8, entry for 't' input field
> - reverse reasoning is explained in the second half of 22.7
>
Small correction. 'time' is just an unsigned integer number (at least 64 bits 
in standard Verilog, exactly 64 bits in SystemVerilog). 'realtime' is just a 
real number.

> I guess '#1ns' statement should introduce the same delay in every
> module, but transferring time between modules is simply sending a number
> without any units.
>
Exactly right.

Martin