Re: [Iverilog-devel] Time in VHDL

[Stephen W. <st...@ic...>]

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On 06/01/2015 08:16 AM, Maciej Sumiński wrote:
> All I need is to use the same timescale in simulated modules. For
> the moment there is no constraint coming from the modules I am
> trying to simulate, so even without introducing any changes
> regarding the timescale in vhdlpp I am still going to be content.
> Simply setting a sensible default timescale will work for me.

If you only need your specific timescale to apply to your modules,
then you should use a module specific timescale. The problem with
the `resetall directive it that the consequences leak out of your
modules to the rest of the design, and affect more than timescale.
Writing your own `timescale directive also leaks out of your modules
into the design at a whole, in unpleasant ways. I think that the
timescale of VHDL code should not effect the timescale of Verilog
code, so you need to do something that has better scope rules.

It is perfectly OK, even expected, that modules have different
timescales, it's just that the `timescale directive is horrible
and that is why SystemVerilog added the timescale module item.
The scoping rules for that timescale are rational.

What it may come down to is that every module you generate has
a timescale module item.

Note, BTW, that there is a difference between timescale and precision.
Note also that there is not really a big performance consequence for
having too much precision in Icarus Verilog, due to the way it operates
its event queue.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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