Re: [Iverilog-devel] Time in VHDL

[Maciej S. <mac...@ce...>]

Hi Cary,

On 06/01/2015 04:52 PM, Cary R. wrote:
> I have not looked at your pull request, but from what I am reading you may have added code that addresses one of our older feature requests on SourceForge so please look at them.

I have just checked it, but apparently the idea I have implemented had
been rejected previously [1], so I believe I need to retract the
corresponding patch.

> I think `resetall may be a bit heavy handed since it will change the timescale, etc. that future modules/files will see. It seems like the more localized SV additions would be best for setting the scale and precision for only the translated modules. You can then translate the time variables using the local module time scale and the calling module time scale. Depending on the scope of the translation routine (VPI call) the parent of the current scope my not be the calling parent. You first have to find the current module and then the calling module (i.e. iterate up the scope chain looking for a module scope). There should be example code in the "vpi" directory somewhere of this type of search.

All I need is to use the same timescale in simulated modules. For the
moment there is no constraint coming from the modules I am trying to
simulate, so even without introducing any changes regarding the
timescale in vhdlpp I am still going to be content. Simply setting a
sensible default timescale will work for me.

We just need to decide which changes related to timescale handling are
welcome and I am going to remove the rest.

Regards,
Orson

>      On Monday, June 1, 2015 12:56 AM, Maciej Sumiński <mac...@ce...> wrote:
>    
> 
>  On 05/31/2015 09:09 PM, Martin Whitaker wrote:
> [..]
>> However, with that timescale, the largest time that can be represented in 64 
>> bits is ~2.5 hours. To get round this (and to avoid slowdown due to 
>> unnecessary precision), the VHDL standard allows a different time resolution 
>> to be specified when a model is elaborated. Other simulators support this via 
>> a configuration file or command line option. Hence my suggestion to use 
>> `resetall at the start of each translated compilation unit and use the 
>> existing iverilog +timescale option to set the default timescale.
>>
>> Martin
> 
> Ok, I think this actually fulfills my needs. Thank you for the
> suggestion and explanation.
> 
> Steve, what is your opinion? Shall I remove the option to specify
> timescale as a iverilog parameter [1] and replace matching timescale for
> VHDL files [2] with default `resetall directive?
> 
> Regards,
> Orson
> 
> 1.
> https://github.com/orsonmmz/iverilog/commit/06864ebd3fbc38f4e2daffcc2d20092c73066da3
> 2.
> https://github.com/orsonmmz/iverilog/commit/250253baf085bf6426eca6b73c03ca78ed584f5e
> 
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