Re: [Iverilog-devel] Time in VHDL

[Maciej S. <mac...@ce...>]

On 05/31/2015 09:09 PM, Martin Whitaker wrote:
[..]
> However, with that timescale, the largest time that can be represented in 64 
> bits is ~2.5 hours. To get round this (and to avoid slowdown due to 
> unnecessary precision), the VHDL standard allows a different time resolution 
> to be specified when a model is elaborated. Other simulators support this via 
> a configuration file or command line option. Hence my suggestion to use 
> `resetall at the start of each translated compilation unit and use the 
> existing iverilog +timescale option to set the default timescale.
> 
> Martin

Ok, I think this actually fulfills my needs. Thank you for the
suggestion and explanation.

Steve, what is your opinion? Shall I remove the option to specify
timescale as a iverilog parameter [1] and replace matching timescale for
VHDL files [2] with default `resetall directive?

Regards,
Orson

1.
https://github.com/orsonmmz/iverilog/commit/06864ebd3fbc38f4e2daffcc2d20092c73066da3
2.
https://github.com/orsonmmz/iverilog/commit/250253baf085bf6426eca6b73c03ca78ed584f5e