Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Stephen Williams wrote:
> System Verilog also allows for per-module timescales. Instead of
> using a compiler directive (which has awful scoping rules) there
> are the timescale and related keywords that can be included as
> module items. Perhaps this is what is needed?

Doesn't really help. The SV per-module timescales don't let you do anything 
you can't do with `timescale - they just have better scoping rules (allowing 
`timescale to persist beyond a compilation unit was just insane).

VHDL doesn't have any concept of timescale and has a default time resolution 
of 1fs. So to mimic VHDL behaviour, all the translated code should have a 
timescale of 1fs/1fs. This would allow time values to be freely passed between 
modules in the translated code.

However, with that timescale, the largest time that can be represented in 64 
bits is ~2.5 hours. To get round this (and to avoid slowdown due to 
unnecessary precision), the VHDL standard allows a different time resolution 
to be specified when a model is elaborated. Other simulators support this via 
a configuration file or command line option. Hence my suggestion to use 
`resetall at the start of each translated compilation unit and use the 
existing iverilog +timescale option to set the default timescale.

Martin