Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Maciej Sumiński wrote:
> I am afraid there is no good solution to the problem due to the fact how
> time values are handled in (System)Verilog.
>
> Instead of using automatically matched timescale, I could use a constant
> `timescale for every VHDL file, no matter what values are used inside.
> Then it might be wrong for files that use e.g. seconds or femtoseconds.
>
> If I understand correctly how `resetall and +timescale work, the effect
> would be the same as if I forced a single timescale for every VHDL file
> with default `timescale directive.

The difference is that by using `resetall and +timescale, the user can 
override the default if it is wrong for their design. A quick glance indicates 
this is what other simulators do for VHDL designs.

With a default time scale/precision of 1ps/1ps, a 64-bit time value can 
represent a delay range of 1ps to 2500 hours, which is likely to cover most 
users needs.

The other simulators I've looked at all default to a precision of 1fs for VHDL 
designs.

> It also means that problem would
> persist for SV modules with their own timescales.

Yes, but native SV modules would expect time variables to contain scaled 
times, because SV doesn't support anything else. If a user is doing mixed-mode 
simulation, they have to take this into account.

Martin