Re: [Iverilog-devel] Time in VHDL

[Martin W. <mai...@ma...>]

Cary R. wrote:
> Hi Orson, We should look at the standard because this could be a bug in
> Icarus, though I certainly understand how it could have been missed in
> Icarus, the standard or other simulators. My analysis is that in the main
> module since the time scale is 1ps we have a value of 1,000 in the a
> variable. It is possible that time variables that are passed are not to be
> scaled as the current behavior does or it could be that we are supposed to
> scale the value using the caller and called routines time scale and
> precision. Depending on how VHDL time variables work we could end up with a
> difference because of the scaling that Verilog specifies.
>
The 'time' data type in Verilog (and SystemVerilog) is a simple integer data 
type with no special semantics. If you pass a time value to a module with a 
different time scale, you have to scale it yourself - the language does 
nothing to help you.

I've verified that the big 3 simulators all give the same result as Icarus for 
Orson's example.

> We absolutely cannot just start putting arbitrary time scales or precisions
> on modules to make things work if they have already been given a timescale
> directive since that changes how time values are scaled/rounded in the
> module and that must work as specified by the standard (e.g. lets say you
> have a raw delay of #1.1 in the called routine).

Maybe the solution to Orson's problem is for vhdlpp to issue a `resetall at 
the start of each translated file and use the existing iverilog +timescale 
option to set the required timescale. We might want to choose a smaller 
default timescale in this case (e.g. 1ps/1ps rather than 1s/1s).

Martin