[Iverilog-devel] Time in VHDL

[Maciej S. <mac...@ce...>]

Hi,

I am looking for the best way to implement expressions related to time
in vhdlpp. Ideally, I would use SystemVerilog's time literals, so:

  wait for 10 ns;

is translated to:

  #10ns;

This ought to be trivial with the current ivl version. The only obstacle
I face now is to support constants, like:

  constant a : time := 10 ns;

The problem here is how to use them in SystemVerilog modules that may
have different time scales.

* First option
One solution that is easy for me to implement is to prepare an
Icarus-specific function that takes mantissa and exponent to describe a
time period:

  localparam a = $ivl_time(10, -9);

Then during elaboration the value would be adjusted according to the
time scale of scope where it is used.

* Second option
While the first approach satisfies my needs, there might be a solution
that you find more advantageous. It also does not introduce any
Icarus-specific functions.

Though it is not available at the moment, it should be fairly easy to
make localparam accept time literals, so the initial example becomes:

  localparam a = 10ns;

but the current implementation stores time as floating point numbers
adjusted to the time scale of the scope where a delay was defined [1].

In order to use a localparam value in a scope that uses a different time
scale, the absolute time value has to be preserved and adjusted during
elaboration (just like $ivl_time would do). To do so, I may either
introduce a new type (veritime?), or assume time values are saved in
femtoseconds.

Do you have any thoughts/preference?

Regards,
Orson

1. https://github.com/steveicarus/iverilog/blob/master/parse.y#L2782