Re: [Iverilog-devel] vhdlpp update

[Maciej S. <mac...@ce...>]

On 04/26/2015 05:33 PM, Stephen Williams wrote:
[..]
> You have a point that TRUE and FALSE may be enumeration values.
> It turns out that they are, and they are defined in the BOOLEAN
> type enumeration in the standard package. Orson, this is something
> you need to take note of. While they are not keywords, they ARE
> predefined enumeration values. There is infrastructure in vhdlpp
> for predefining types, that is what you want to use here.

Thank you for the suggestion. I have updated the branch [1] and extended
its test [2] to check logical operators.

To simplify things, I kept boolean type as VTypePrimitive instead of
VTypeEnum, and simply generated a header:

`ifndef __VHDL_STD_TYPES
`define __VHDL_STD_TYPES
typedef enum bit { \false , \true } boolean ;
`endif

It is important to use directives here to avoid multiple definitions.
Alternatively, I could turn boolean type into VTypeEnum, but I would
still need directives to have it defined only once, so I am not sure if
this could look better in the code (i.e. a dedicated if to output
boolean definition).

Unfortunately, this will not allow evil designers to name their signals
'true' and 'false', because even if VHDL accepts it, SystemVerilog is a
little bit more sane and objects to signals and enum values having the
same name.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/67
2. https://github.com/orsonmmz/ivtest/tree/boolean_test