Re: [Iverilog-devel] vhdlpp update

[Kevin C. <iv...@gr...>]

The whole keyword thing is just a consequence of how people did parsers - if you use context aware recursive-descent parsers then there isn't a problem.

One useful thing that VHDL does is that it moved a lot of stuff to user-space by putting it in "standard headers". You don't have to take the LRM literally, and you can move things like "true" & "false" to enum in a header file.

The LRMs are really just statements of what you need to understand to be compatible, you can implement your version with more/better capabilities.

Kev.

On 04/23/2015 08:35 AM, Stephen Williams wrote:
> On 04/23/2015 07:16 AM, Maciej Sumiński wrote:
> > I have one doubt regarding the proposed branch. It introduces a few
> > new keywords (true, false, note, warning, error, failure). Because
> > of that, it is impossible to use them as names, so for example you
> > cannot have a signal called 'true', which should be technically
> > valid according to the VHDL standard.
>
> If the word is not a reserved word as listed in the IEEE1076
> standard, then it cannot be parsed as a keyword. It needs to
> be matched as an IDENTIFIER and interpreted during semantic
> analysis. This is one of the painful quirks of VHDL.
>
> So no, you cannot add new keywords. Match them as IDENTIFIERs,
> then check the actual value in the rules where you expect them.
>
>
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