Re: [Iverilog-devel] vhdlpp update

[Martin W. <mai...@ma...>]

Maciej Sumiński wrote:
> I enclose one more patch that needs a review. I am wondering if it is
> required for both arguments in NetEBDiv to have the same width? There is
> a testcase attached which causes an assertion failure, but in fact it
> works fine. It also does not break any other tests, but I might have
> missed something important there.
>
The steps required for expression evaluation in Verilog are:

   - determine the width of the expression, according to the rules
     in the standard

   - extend all operands to the width of the expression, using
     the type of the expression (unsigned/signed), not the
     type of the operands, to decide whether to zero extend
     or sign extend

   - evaluate the expression

If you don't make sure all the operands are the same size before evaluating 
the expression, most of the time you'll get the same result, but there will be 
corner cases where you don't.

Martin