Re: [Iverilog-devel] vhdlpp update

[Stephen W. <st...@ic...>]

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On 04/24/2015 06:42 AM, Maciej Sumiński wrote:
> I enclose one more patch that needs a review. I am wondering if it
> is required for both arguments in NetEBDiv to have the same width?
> There is a testcase attached which causes an assertion failure, but
> in fact it works fine. It also does not break any other tests, but
> I might have missed something important there.

The assertions you want to remove are in the eval_tree(...) method
of the NetEBDiv node, which evaluates the division/mod expression.
The problem here is that the verinum divide (/ and %) operators
kinda assume that the operands and the result are the same size.
The assert is apparently there because the consequences of passing
mismatched arguments to these operators will not have predictable
results, and doesn't handle the various consequences.

The way forward to removing the asserts involves adjusting the
operands so that their sizes match the output size (cast_to_width
should help you there) first, then do the divide.

Otherwise, I do not think there are constraints that the divide
operand sizes must match, so the above approach should do it
for you.


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