[Iverilog-devel] vhdlpp update

[Maciej S. <mac...@ce...>]

Hi,

There is a new branch [1, 2] that contains new features for vhdlpp:
- assertion & report statements
- boolean type (to be more precise: "true" & "false" values)
- fixes missing std_logic values in emit() functions

I have one doubt regarding the proposed branch. It introduces a few new
keywords (true, false, note, warning, error, failure). Because of that,
it is impossible to use them as names, so for example you cannot have a
signal called 'true', which should be technically valid according to the
VHDL standard.

Alternatively, I could detect the keywords with strncmp() in appropriate
rules in the parser. Is it the preferred approach or is there another
more elegant solution to the problem?

I am also wondering if there is a way to translate weak std_logic values
('L', 'H' & 'W') to SystemVerilog. I know there is 'strength' property,
but it is not exactly the same (e.g. it cannot be used to compare to a
net value).

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/61
2. https://github.com/orsonmmz/ivtest/tree/asserts_test