Re: [Iverilog-devel] iverilog - constant user function.

[Martin W. <mai...@ma...>]

dp...@sw... wrote:

 >> Most likely something inside the module is also assigning a value to R.
>
> My code structure bellow:
> core_rst is defined as output in module1, and R is input in a few ODDR2
> modules I instantiate in the main_module
> However R is defined with a ‘pulldown’ and I guess this explains the
> warning?
> ODDR2 Is from standard Xilinx
> /opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/ODDR2.v
>
Yes, the pulldown will cause this.

Labelling a port as "input" in Verilog does not do what you would expect it 
to. You might find these of help:

 
http://www.sutherland-hdl.com/papers/2006-SNUG-Boston_standard_gotchas_paper.pdf

   http://www.sutherland-hdl.com/papers/2007-SNUG-SanJose_gotcha_again_paper.pdf

Martin