Re: [Iverilog-devel] iverilog for syntesis

[Martin W. <mai...@ma...>]

dp...@sw... wrote:
> Hello,
>
> I am trying to use Icarus Verilog for implementation of my Verilog HDL in Xilinx xc6slx9-tqg144-2 target.
>
> I can successfully compile for a simulation target with the line
> iverilog -o DSLogic -I ./src/i2c/ -y ./ISE/unisims/  ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v ./ISE/Verilog/src/glbl.v $(MY_VERILOG_FILES)
>
> What is the command I should use to get data suitable for the Xilinx ngdbuild tool?
>
iverilog is primarily a simulator. It has some very basic synthesis 
capabilities, but not enough for serious use as a synthesis tool. Your easiest 
option is to use the Xilinx synthesis tool (Xst) - you will have to use the 
Xilinx tools anyway for place&route and bitstream generation. If you do want 
to experiment with open-source alternatives, 
http://www.clifford.at/yosys/about.html is a possibility (although not one 
I've tried myself).

Martin