Re: [Iverilog-devel] iverilog - constant user function.

[<dp...@sw...>]

Hello

>> I am getting few warnings however.
>> Please ignore if this is not the best place to ask such a questions.

>This list is really for discussing things specific to Icarus Verilog - you
>might try comp.lang.verilog for more general questions. But a few quick 
>comments:

>> ./src/DSLogic_top.v:315: warning: input port R is coerced to inout.
>> I have confirmed that R s an input which is supplied by the output of 
>> other module.
>> Any typical reasons we could get this ‘coerced’ issue?

>Most likely something inside the module is also assigning a value to R.

My code structure bellow:
core_rst is defined as output in module1, and R is input in a few ODDR2 
modules I instantiate in the main_module
However R is defined with a ‘pulldown’ and I guess this explains the 
warning?
ODDR2 Is from standard Xilinx 
/opt/Xilinx/14.7/ISE_DS/ISE/verilog/src/unisims/ODDR2.v

module   main_module ()
...
wire core_rst;
...
module1 module1(..., .core_rst(core_rst), ...) //core_rst is defined as 
output in module1
module2 module2(..., .core_rst(core_rst), ...) //core_rst is defined as 
input in module2
module3 module3(..., .core_rst(core_rst), ...) //core_rst is defined as 
input in module3
...
ODDR2 #(
      .DDR_ALIGNMENT("C0"),
      .INIT(1'b0),
    .SRTYPE("ASYNC")
) trig_oe_oddr (
      .Q(ext_trig_oe_oddr),
      .C0(adc_clkb),
      .C1(~adc_clkb),
      .CE(1'b1),
      .D0(~ext_pin_oe),
      .D1(~ext_pin_oe),
      .R(core_rst),       // <= coerced  warning referring here, R is 
defined as input in
      .S(1'b0)
);

ODDR2 #(
      .DDR_ALIGNMENT("C0"),
      .INIT(1'b0),
    .SRTYPE("ASYNC")
) clk_oe_oddr (
      .Q(ext_trig_oe_oddr),
      .C0(adc_clkb),
      .C1(~adc_clkb),
      .CE(1'b1),
      .D0(~ext_pin_oe),
      .D1(~ext_pin_oe),
      .R(core_rst),         // <= coerced  warning referring here
      .S(1'b0)
);

...

end

Best Regards
Dimitar