[Iverilog-devel] iverilog for syntesis

[<dp...@sw...>]

Hello,

I am trying to use Icarus Verilog for implementation of my Verilog HDL in Xilinx xc6slx9-tqg144-2 target.

I can successfully compile for a simulation target with the line
iverilog -o DSLogic -I ./src/i2c/ -y ./ISE/unisims/  ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v ./ISE/Verilog/src/glbl.v $(MY_VERILOG_FILES)

What is the command I should use to get data suitable for the Xilinx ngdbuild tool?

Thanks,
Dimitar