Re: [Iverilog-devel] iverilog - constant user function.

[Martin W. <mai...@ma...>]

dp...@sw... wrote:
> I am getting few warnings however.
> Please ignore if this is not the best place to ask such a questions.

This list is really for discussing things specific to Icarus Verilog - you 
might try comp.lang.verilog for more general questions. But a few quick comments:

> ./src/DSLogic_top.v:315: warning: input port R is coerced to inout.
> I have confirmed that R s an input which is supplied by the output of other module.
> Any typical reasons we could get this ‘coerced’ issue?

Most likely something inside the module is also assigning a value to R.

> ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v:3202: warning: @* found no sensitivities so it will never trigger.
> This is on the line 3202
> ...
> always @* rst_full_gen_i <= 1'b0;
> ...
> I guess this is more an issue of ./ISE/XilinxCoreLib/FIFO_GENERATOR_V8_2.v as we assigned constant here, so no sensitivity?

Yes, this assignment will never get executed because there is nothing to 
trigger the always statement.

Martin