Re: [Iverilog-devel] Assertion failure for system verilog structs

[Cary R. <cy...@ya...>]

Hi Martin,
I'm guessing that the difference is $display can work with automatic variables and things like $strobe (which also fails) and $monitor cannot so we have to check to see if the variable is automatic. I think the problem is that between step 5 and 6 the reference to the net is being lost while trying to determine if the argument is to an automatic variable (or in this case part of an automatic variable) or not. It almost looks like we are loosing the pointer to the parent for the PV structure, vvp_lookup_handle() is failing? We would need to run this with a runtime compiled with -O0 and -g to get the true back trace.

 Cary


     On Monday, March 16, 2015 3:16 PM, Martin Whitaker <mai...@ma...> wrote:
   

 ni...@ly... (Niels Möller) wrote:
> Martin Whitaker <mai...@ma...> writes:
>
>> I have reproduced the first failure, but not the second. Could you provide a
>> simple test case that demonstrates it?
>
> It seems a bit tricky to reproduce, I also don't see the problem with my
> current code. Maybe it's not really related to structs, I don't know.
>
Yes, it's a more general problem. Reducing your code, I ended up with this:

  wire [7:0] my_net;

  assign my_net[3:0] = 1;

  initial begin
    #1 $monitor("At time %0t, field1 = %h", $time, my_net[3:0]);
    #1 $finish;
  end

Passing a part select of a wire to $monitor seems to be the issue. $display 
doesn't have the problem.

This code works in v0.9, so it's a regression.

Martin

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