Re: [Iverilog-devel] Assertion failure for system verilog structs

[Martin W. <mai...@ma...>]

ni...@ly... (Niels Möller) wrote:
> Martin Whitaker <mai...@ma...> writes:
>
>> I have reproduced the first failure, but not the second. Could you provide a
>> simple test case that demonstrates it?
>
> It seems a bit tricky to reproduce, I also don't see the problem with my
> current code. Maybe it's not really related to structs, I don't know.
>
Yes, it's a more general problem. Reducing your code, I ended up with this:

   wire [7:0] my_net;

   assign my_net[3:0] = 1;

   initial begin
     #1 $monitor("At time %0t, field1 = %h", $time, my_net[3:0]);
     #1 $finish;
   end

Passing a part select of a wire to $monitor seems to be the issue. $display 
doesn't have the problem.

This code works in v0.9, so it's a regression.

Martin