[Iverilog-devel] iverilog - constant user function.

[<dp...@sw...>]

Hi All,

I am new to Verilog Xilinx and iverilog. 
I have made a design which builds OK in Xilinx ISE.

I am tiring to test if I can build this in Linux using iverilog.  

I am at the point now getting 

FIFO_GENERATOR_V8_2.v:3336: sorry: constant user functions are not currently supported: log2_val().
This is the original file from the Xilinx ISE 
Xilinx\14.7\ISE_DS\ISE\verilog\src\XilinxCoreLib\FIFO_GENERATOR_V8_2.v

Can you please give me some hint solving this ?

Assuming I manage to fix this is there a comand line tools in Linux able to implement bitstream for Xilinx XC6SLX9 devices

Thanks
Dimitar