Re: [Iverilog-devel] Update

[Maciej S. <mac...@ce...>]

I had to correct the previous implementation for accessing constant
arrays of vectors. I did not realize that ranges in part selection have
to be constant, and variables are simply forbidden even if the
difference between indices is constant. This makes the solution useless
if one wants to implement e.g. a multiplexer.

New pull request [1] resolves the problem by expanding the right side
value to a concatenation of selected signals. Also, the method has been
improved to handle constant records (and arrays of records or any other
combination).

There are $ivlh_{rising,falling}_edge() VPI functions to implement
VHDL's rising_edge() and falling_edge().

Attributes are evaluated to constants whenever possible. Thanks to that
it is possible to use quite common expressions as 'left and 'right as
index. Also generic parameters are evaluated whenever possible, as I
have found at least one case where the evaluation helped.

All the mentioned changes are supported with tests [2].

Have a nice weekend,
Orson

1. https://github.com/steveicarus/iverilog/pull/55
2. https://github.com/orsonmmz/ivtest/tree/const_record_test