[Iverilog-devel] Update

[Maciej S. <mac...@ce...>]

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Hi Steve,

I have another update[1] along with tests[2] that brings:
- - enum can be used as a port type in modules (SystemVerilog)
- - shift operators (SRL/SLL/SRA/SLA) (VHDL)
- - labeled assignments (VHDL)
- - fixed accessing words in constant arrays of vectors (VHDL)
- - 'natural' type translated as 'int unsigned' (VHDL)
- - a bunch of minor fixes

The implementation of the fourth point may seem a bit twisted,
therefore deserves a word of explanation:

Currently, constant arrays of vectors are flattened to single
one-dimensional localparams, as there is no support for constant
unpacked arrays. Therefore, if the user wants to access a particular
word, then it is necessary to extract the adequate part of the
localparam, and it is done by adjusting the indices. Without the
adjustment, only a single bit would be returned.
To give an example:

== VHDL ==
type uns_array is array (natural range <>) of unsigned(7 downto 0);

constant const_array : uns_array(2 downto 0) :=
    (0 => "00110011", 1 => "101010101", 2=> "00001111");

target_var := const_array(1);

== SystemVerilog ==
localparam const_array = { 8'b00110011, 8'b10101010, 8'b00001111 };

target_var = const_array[15:8]; // <- indices adjusted to pick the word

It can be easily changed once the unpacked constant arrays are supported.

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/54
2. https://github.com/orsonmmz/ivtest/tree/const_array_test
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