[Iverilog-devel] System Verilog and interfaces

[<ni...@ly...>]

Speaking of System Verilog and interfaces, what's the current status of
System Verilog support?

Consider the first example on
http://www.doulos.com/knowhow/sysverilog/tutorial/interfaces/, which
could be cut down a bit to the following:

  // Interface definition
  interface Bus;
    logic [7:0] Addr, Data;
    logic RWn;
  endinterface
  
  module RAM (Bus MemBus); /* ! */
  endmodule

This gives a syntax error on the line marked /* ! */,

  $ iverilog -g2005-sv interface.vl
  interface.vl:7: syntax error
  interface.vl:7: Errors in port declarations.

I had a quick look in the source code, and I see nothing in parse.y to
allow a named interface as a data type. I'm a bit in the dark as to how
these things work. Maybe pform.cc:pform_test_type_identifier should look
up known interfaces? In the grammar for the non-terminal
port_declaration, it looks like a named interface, which I guess is just
an IDENTIFIER to the lexer, ought to be parsed as part of the
data_type_or_implicit non-terminal.

Currently, it seems defining an interface (at top-level) adds the
interface to pform_modules, as an instance of Module with is_interface
== true. While defining other types (typedef, struct, or class) adds an
entry to pform_typedefs.

Regards,
/Niels

-- 
Niels Möller. PGP-encrypted email is preferred. Keyid C0B98E26.
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