[Iverilog-devel] Unbounded vectors in VHDL functions

[Maciej S. <mac...@ce...>]

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Hereby I would like to gleefully announce that I have just completed
the quest for the Unbounded Vectors in Functions in VHDL [1,2]. It was
the most challenging task so far, and even though the path was long
and full of thorns, the Mt Doom is still far ahead. Drenched with
faith, I continue the adventure to confront VHDL gremlins..

It turned out that casting between dynamic arrays and vectors does not
solve the problem, as it requires dynamic memory allocation which is not
feasible for continuous assignments. Maybe it could have been solved
with a bit of VPI sorcery, but the gain is not worth it.

Once I had implemented the mentioned solution and discovered its
problem, I switched to the other idea: function instances. It also has
its limitations, but IMHO much more reasonable. It will not allow to
return vectors of different sizes, if the size depends on the execution
path. For example:

if a > b then
  return B"1001";
else
  return B"1001010101";

Fortunately, I have never seen such code in real-life examples.

One minor addition is support for case statements alternatives with
multiple choices in VHDL (e.g. "when A|B|C|D =>").

The pull request also includes the previously proposed changes (mostly
related to type casting and dynamic arrays in SystemVerilog), with one
problematic commit excluded (dynamic arrays with words of arbitrary size).

Regards,
Orson

1. https://github.com/steveicarus/iverilog/pull/52
2. https://github.com/orsonmmz/ivtest/tree/unbounded_function_test
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