Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

A patch for this has been pushed to git.
The issues was that zero replications inside of concatenations were generating incorrect vvp code for the new stack based vector operators. For the moment this code checks to see if the sub-expression width is zero. A more specific fix would check to see if the sub-expression was a concatenation that had a zero replication. I can easily change the code if needed, but the zero width may be better if other things can also generate a zero width result. I don't know of any, but there may be SystemVerilog constructs that can do this. Does anyone have an opinion on this or know of a construct that can do this?
Cary 

     On Monday, February 2, 2015 10:20 AM, Cary R. <cy...@ya...> wrote:
   

 Hi Lonnie,
I was able to reduce this example down even further. It looks like the problem is that when Steve switched to the new stack code something broke concerning zero replications. At the moment an input width of 32 is getting a sign bit added which gives a width of 33 instead of 32. I will try to look at this later today.

Cary
 

     On Monday, February 2, 2015 9:03 AM, Lonnie Gliem <lg...@sr...> wrote:
   

 Hi Cary,
I found the code causing the error and have attahced a small verilog
file that causes it. 

iverilog iverilog_core.v 

Then run it. 
[lgliem@ajax ulogic_sim]$ ./a.out
Fun: 0x7ba500 is for variable clk
Fun: 0x7ba550 is for variable data_in_tmp
Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
vvp: vvp_net_sig.cc:185: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.
Aborted (core dumped)

Lonnie