Re: [Iverilog-devel] vvp runtime error

[Lonnie G. <lg...@sr...>]

Hi Cary,
I found the code causing the error and have attahced a small verilog
file that causes it. 

iverilog iverilog_core.v 

Then run it. 
[lgliem@ajax ulogic_sim]$ ./a.out
Fun: 0x7ba500 is for variable clk
Fun: 0x7ba550 is for variable data_in_tmp
Current vector is:32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
New value is:33'bZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ
vvp: vvp_net_sig.cc:185: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.
Aborted (core dumped)

Lonnie