Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

The iverilog flag Steve mentioned is -pfileline=1. This will help if the problem is in the procedural code, but does nothing for continuous assignments.
Cary 

     On Wednesday, January 28, 2015 1:10 PM, Stephen Williams <st...@ic...> wrote:
   

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That is the runtime griping that a value assigned into it
(either by procedural assign or passing through the netlist)
is not the expected size or format. That is probably a code
generator problem. You may try turning on line-by-line debug
printing (the vvp code generator can do this for you, I forget
the exact command line flags.) and see what kind of assignment
does this to you.

On 01/28/2015 12:20 PM, Lonnie L Gliem wrote:
> -v: vvp_net_sig.cc:181: virtual void 
> vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&, 
> void**): Assertion `bit.size() == bits4_.size()' failed.

- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com          But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
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