Re: [Iverilog-devel] vvp runtime error

[Cary R. <cy...@ya...>]

Hi Lonnie,
It did appear multiple times. I believe the list software does not send you a copy, but if you look in the archives it is usually there.
The issue you are experiencing is that somehow a value is being put to a signal and the width of the value does not match the width of the signal. You may be able to get some information to narrow this down by printing the various state information before the assert() (e.g. the actual current and new bit values/size, etc.). That should allow you to then try to debug this down to a specific piece of Verilog code. This can often be fairly convoluted (e.g. a signal passed to a port with a specific type of driver, etc.), so it's not always easy to create a small/simple example.
I can help you off list if needed, but without the source code you are going to need to do most of the basic debug work.
Have you tried this with other version to see if this is just a problem in that snapshot?

These problems are often a bug in the code generated by the compiler for corner cases that are not handled correctly.
Cary
 

     On Wednesday, January 28, 2015 12:45 PM, Lonnie L Gliem <lg...@sr...> wrote:
   

 <!--#yiv0649106253 _filtered #yiv0649106253 {font-family:Calibri;panose-1:2 15 5 2 2 2 4 3 2 4;} _filtered #yiv0649106253 {font-family:Tahoma;panose-1:2 11 6 4 3 5 4 4 2 4;}#yiv0649106253 #yiv0649106253 p.yiv0649106253MsoNormal, #yiv0649106253 li.yiv0649106253MsoNormal, #yiv0649106253 div.yiv0649106253MsoNormal {margin:0in;margin-bottom:.0001pt;font-size:11.0pt;font-family:"Calibri", "sans-serif";}#yiv0649106253 a:link, #yiv0649106253 span.yiv0649106253MsoHyperlink {color:blue;text-decoration:underline;}#yiv0649106253 a:visited, #yiv0649106253 span.yiv0649106253MsoHyperlinkFollowed {color:purple;text-decoration:underline;}#yiv0649106253 span.yiv0649106253EmailStyle17 {font-family:"Calibri", "sans-serif";color:windowtext;}#yiv0649106253 span.yiv0649106253EmailStyle18 {font-family:"Calibri", "sans-serif";color:#1F497D;}#yiv0649106253 .yiv0649106253MsoChpDefault {font-size:10.0pt;} _filtered #yiv0649106253 {margin:1.0in 1.0in 1.0in 1.0in;}#yiv0649106253 div.yiv0649106253WordSection1 {}-->Hi Cary,I tried posting this to the iverilog devel list but I don’t think it’s working so thought I would try sending it direct to you. ThanksLonnie   From: Lonnie L Gliem [mailto:lg...@sr...] 
Sent: Wednesday, January 28, 2015 2:21 PM
To: 'ive...@li...'
Subject: vvp runtime error  Sorry if this is a multiple posting but I never saw the last one.I started getting a runtime error with 20150105 snapshot. Can someone tell me how to get more info on what it is blowing up on. Here is the error.   -v: vvp_net_sig.cc:181: virtual void vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&, void**): Assertion `bit.size() == bits4_.size()' failed.