[Iverilog-devel] Error at runtime

[Lonnie G. <lg...@sr...>]

I am getting a runtime error and was wondering if there is anyway I can
get somemore info on what it is vlowing up on. 

Here is the error:
-v: vvp_net_sig.cc:181: virtual void
vvp_fun_signal4_sa::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
void**): Assertion `bit.size() == bits4_.size()' failed.

Thanks
Lonnie