Re: [Iverilog-devel] Is there any way to avoid this shift/reduce conflict?

[<ni...@ly...>]

Pete Johnson <pe...@be...> writes:

> What you suggest is not how the mod port syntax works. It uses the
> keywords “input” and “output”, not “in” and “out”. Here is an example
> from the standard
>
> interface i2;
> wire a, b, c, d;
> modport master (input a, b, output c, d);
>
> modport slave (output a, b, input c, d);
>
> endinterface

Thanks for the example. That makes it a lot easier to follow the
discussion for those of us not familiar with system verilog.

One question: Is the grouping of a,b and c,d essential, or is "(input a,
b, output c, d)" just a shorthand for "(input a, input b, output c,
output d)"?

In the latter case, it would make sense to me to make it a single list
of entries where the port_direction is optional, and then have some
semantic rules (i.e., not really part of the grammar) which (i)
remembers the most recent port_direction and applies it to following
entries, and (ii) generates a syntax error in case the first entry is
missing a port_direction. (Not sure if part (ii) is easy to express in
the grammar, if it is, then that's preferable of course).

Regards,
/Niels

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