Re: [Iverilog-devel] do while loop syntax.

[Cary R. <cy...@ya...>]

Are you telling Icarus to use SystemVerilog (e.g. -g2009, -g2012 or -g2005-sv)? The following example runs correctly (displays 0 to 9) using the latest code from git and the -g2009 flag:
module top;
  integer val;

  initial begin
    val = 0;
    do begin
      $display(val);
      val += 1;
    end while (val < 10);
  end
endmodule
Since SystemVerilog is not that complete in Icarus it is not enabled by default.

Cary
 

     On Thursday, January 8, 2015 1:17 PM, Lonnie Gliem <lg...@sr...> wrote:
   

 What is the do while syntax for iverilog. I have the loop below that
compiles fine in vcs but errors out in iverilog.

do begin
    @(posedge clk);
    err = $carte_accept(listening_sockfd);
end while (err == -1);

Here are the errors.

/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:87:
syntax error
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:88:
error: malformed statement
/home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:95:
syntax error

Here is the version:

Icarus Verilog version 0.10.0 (devel) (s20140801-15-g4ea512c)

Thansk for the help
Lonnie


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