From: Lonnie G. <lg...@sr...> - 2015-01-08 21:16:43
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What is the do while syntax for iverilog. I have the loop below that compiles fine in vcs but errors out in iverilog. do begin @(posedge clk); err = $carte_accept(listening_sockfd); end while (err == -1); Here are the errors. /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:87: syntax error /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:88: error: malformed statement /home/dvl/installs/TRIAL_5.3_64/opt/srcci/comp/lib/macros/map_m/v/eth_command_accept.v:95: syntax error Here is the version: Icarus Verilog version 0.10.0 (devel) (s20140801-15-g4ea512c) Thansk for the help Lonnie |