[Iverilog-devel] Is there any way to avoid this shift/reduce conflict?

[Martin W. <mai...@ma...>]

I'm trying to add support for SystemVerilog modports to the iverilog parser. 
The relevant snippet from parse.y looks like this:

modport_item
   : IDENTIFIER
       { pform_start_modport_item(@1, $1); }
     '(' modport_ports_list ')'
       { pform_end_modport_item(@1); }
   ;

modport_ports_list
   : modport_ports_declaration
   | modport_ports_list ',' modport_ports_declaration
   ;

modport_ports_declaration
   : attribute_list_opt port_direction modport_simple_port_list
       { pform_add_modport_ports(@2, $1, $2, $3); }
   | attribute_list_opt import_export modport_tf_port_list
       { ... }
   | attribute_list_opt K_clocking IDENTIFIER
       { ... }
   ;

modport_simple_port_list
   : IDENTIFIER
       { $$ = make_port_list($1, 0); }
   | '.' IDENTIFIER '(' expression ')'
       { $$ = make_port_list($2, $4); }
   | modport_simple_port_list ',' IDENTIFIER
       { $$ = make_port_list($1, $3, 0); }
   | modport_simple_port_list ',' '.' IDENTIFIER '(' expression ')'
       { $$ = make_port_list($1, $4, $6); }
   ;

which is giving me a shift/reduce conflict. The problem is the parser can't 
distinguish between a ',' that separates items in a modport_simple_port_list 
and one that separates items in a modport_ports_list.

I can't find a way to avoid the conflict with a single level of lookahead. Can 
anyone else?