Re: [Iverilog-devel] vec4-stack merge

[Cary R. <cy...@ya...>]

As was likely expected the vec4-stack changes broke compiling with valgrind support. I will work on that and look for memory leaks in the new code later.
A critical issues is that 32-bit support is broken, some tests are failing and one (pr1625912) is locking up in an infinite loop. I will look at fixing this as soon as I have some free time. Hopefully later today or tomorrow.

Cary 

     On Tuesday, December 9, 2014 6:03 PM, Cary R. <cy...@ya...> wrote:
   

 No example, but a patch has been pushed that fixes the problems in the non-blocking assignment to array words. There were a few cases where it was more than just extra code being generated since the error state was being partially lost. I didn't generate actual tests for testing this, but checked many combinations to verify that the generated code looked correct. The errors were related to having both a variable array index and variable part select offset (indexed part select). There are still a few cases where some extra flag code is begin generated, but it should be fully functional now.

There is still extra flag code being generated for a blocking constant part select assignment to an array word, but all the combinations appear to be generating correct code.
Cary 

     On Tuesday, December 9, 2014 8:30 AM, Stephen Williams <st...@ic...> wrote:
   

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On 12/08/2014 09:41 PM, Cary R. wrote:
> It also looks like the compiler generated code for array accesses
> may be doing more work than is required. It is using flag 4 to
> indicate an undefined index (a predicate flag for the stores), but
> I'm not sure what all the flag 8 control is for since I couldn't
> find where it was actually used.

There are surely going to be cases where the code generator is
not writing optimal code. Now that the vec4-stack code is the
main line, many more eyes is catching stuff like this.

Concrete examples would help.

- -- 
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