Re: [Iverilog-devel] vec4-stack merge

[Stephen W. <st...@ic...>]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1


Awesome! Thanks for the patches.

As for pr1830834, the problem is that before the vec4-stack merge,
there was a vpi special symbol for referencing part selects, so this
was able to work. Sorta. But even at that, it kinda violated the
conceit of the vvp runtime model. I don't really know what do do
about this now, so until we have a good solution, this should print
a "sorry" message.

On 12/07/2014 07:08 AM, Martin Whitaker wrote:
> I've fixed all but one of the new failures, and have also fixed the
> memory leak for user function calls in a continuous assignment
> statement.
> 
> The remaining new failure is pr1830834. A simplified example of the
> problem is
> 
> reg [3:0] i;
> 
> reg [15:0] value = 16'h5555;
> 
> initial begin i = 0; $strobe("Value is %b", value[i+1]); i = 1; 
> end
> 
> With the vec4-stack merge, this results in the following run-time
> error:
> 
> SORRY: test.v:9: currently only simple signals or constant
> expressions may be passed to $strobe.
> 
> Before the merge, the output is
> 
> Value is 0
> 
> The correct result should be
> 
> Value is 1
> 
> The pr1830834 test only worked because it didn't change the index
> variable after $strobe was called.
> 
> I propose we change the regression tests to expect a run-time error
> for this test. Any dissenters?


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2

iEYEARECAAYFAlSEga8ACgkQrPt1Sc2b3ikMJgCfX0hEUMg66ouRwA5EslCrmsP1
cgEAoKL/uOu353BD6kR12zNgS5dk9tNS
=EbA8
-----END PGP SIGNATURE-----