Re: [Iverilog-devel] vec4-stack merge

[Martin W. <mai...@ma...>]

I've fixed all but one of the new failures, and have also fixed the memory 
leak for user function calls in a continuous assignment statement.

The remaining new failure is pr1830834. A simplified example of the problem is

   reg [3:0] i;

   reg [15:0] value = 16'h5555;

   initial begin
     i = 0;
     $strobe("Value is %b", value[i+1]);
     i = 1;
   end

With the vec4-stack merge, this results in the following run-time error:

SORRY: test.v:9: currently only simple signals or constant expressions may be 
passed to $strobe.

Before the merge, the output is

   Value is 0

The correct result should be

   Value is 1

The pr1830834 test only worked because it didn't change the index variable 
after $strobe was called.

I propose we change the regression tests to expect a run-time error for this 
test. Any dissenters?


Stephen Williams wrote:
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> There are indeed a couple new failures, that were I think brought
> on be collisions between the new work and the original fix for
> them. This was bound to happen given that the branch was starting
> to diverge, and could have gotten even worse if I kept on. I tried
> merging master into the vec4-stack as I was going, but that is
> probably where I went wrong.