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From: Martin W. <mai...@ma...> - 2014-12-06 22:38:04
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I'm running in a 64-bit environment. It looks like merge problems - for example the pr3366217b/c/g failures seem to be because some of your enumeration fixes have been lost. I can sort this out if necessary, but will wait to hear from Steve. Cary R. wrote: > Martin, > I haven't synced to the new code, and probably won't for a couple days, but is this a 32-bit vs 64-bit issue? Most people seem to be running and testing under 64-bit, though I still have one setup that is 32-bit to check for this specific problem and I have fixed a few bugs related to that lately. > Cary > > On Saturday, December 6, 2014 11:56 AM, Martin Whitaker <mai...@ma...> wrote: > > > I'm seeing 6 new failures when I run the regression tests: > > % grep Failed regression_report.txt > pr1830834: ==> Failed - output does not match gold file. > analog1: ==> Failed - running iverilog. > analog2: ==> Failed - running iverilog. > fileline2: ==> Failed - output does not match gold file. > pr3366217b: ==> Failed - CE - output does not match gold file. > pr3366217c: ==> Failed - CE (no error reported). > pr3366217g: ==> Failed - CE - output does not match gold file. > br_gh13a: ==> Failed - output does not match gold file. > br605a: ==> Failed - output does not match gold file. > br605b: ==> Failed - output does not match gold file. > if_part_no_else2: ==> Failed - running iverilog. > Total=2087, Passed=2076, Failed=11, Not Implemented=0, Expected Fail=0 > > Are these known issues? > > Stephen Williams wrote: >> -----BEGIN PGP SIGNED MESSAGE----- >> Hash: SHA1 >> >> >> I've gone and done it, I've merged the vec4-stack branch into >> the master branch. This is a BIG set of changes that I've been >> working on for many months now, with the idea of cleaning up >> the vvp runtime and opening up some performance optimization >> opportunities. >> >> For those who care, what I've done is rework the vvp instruction >> set for handling logic vectors. Up until now, the vvp engine >> kept a long vector of "register" space, and operations like add, >> subtract, etc. picked their operands out of that register space. >> After this merge, the register space has been converted into a >> stack of vectors. The instructions just pull operands of the >> stack, so fewer operands are needed, and there is no more picking >> operands out of a larger vector. >> >> I have taken advantage of some of the benefits, some tests should >> now run significantly faster. If you find any things that run >> slower with the new system, I'd like to know about them. >> >> The outputs in some cases are different. The Verilog standard >> has some ambiguous corners and with this merge Icarus Verilog >> may generate for you some different but still legal results, >> mostly related to vector widths. I have updated the regression >> test suite to account for most of these, but you may see some >> subtle differences in your run time results. Should still be legal, >> though, so you should be fine. >> >> >> - -- >> Steve Williams "The woods are lovely, dark and deep. >> steve at icarus.com But I have promises to keep, >> http://www.icarus.com and lines to code before I sleep, >> http://www.picturel.com And lines to code before I sleep." >> -----BEGIN PGP SIGNATURE----- >> Version: GnuPG v2 >> >> iEYEARECAAYFAlSDOgUACgkQrPt1Sc2b3ikesgCg20PgbNMyXz8H3uwOuo9TAH8y >> svMAoKC5oAfKNSu8o6TSENhBKecSYjqo >> =0Ndq >> -----END PGP SIGNATURE----- >> >> ------------------------------------------------------------------------------ >> Download BIRT iHub F-Type - The Free Enterprise-Grade BIRT Server >> from Actuate! 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