[Iverilog-devel] vec4-stack merge

[Stephen W. <st...@ic...>]

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I've gone and done it, I've merged the vec4-stack branch into
the master branch. This is a BIG set of changes that I've been
working on for many months now, with the idea of cleaning up
the vvp runtime and opening up some performance optimization
opportunities.

For those who care, what I've done is rework the vvp instruction
set for handling logic vectors. Up until now, the vvp engine
kept a long vector of "register" space, and operations like add,
subtract, etc. picked their operands out of that register space.
After this merge, the register space has been converted into a
stack of vectors. The instructions just pull operands of the
stack, so fewer operands are needed, and there is no more picking
operands out of a larger vector.

I have taken advantage of some of the benefits, some tests should
now run significantly faster. If you find any things that run
slower with the new system, I'd like to know about them.

The outputs in some cases are different. The Verilog standard
has some ambiguous corners and with this merge Icarus Verilog
may generate for you some different but still legal results,
mostly related to vector widths. I have updated the regression
test suite to account for most of these, but you may see some
subtle differences in your run time results. Should still be legal,
though, so you should be fine.


- -- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."
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