Re: [Iverilog-devel] Handling of constant inputs and unused outputs

[Martin W. <mai...@ma...>]

This is getting a bit off-topic for this list, but I'll risk annoying the 
readership with one more reply...

ni...@ly... (Niels Möller) wrote:
> Martin Whitaker <mai...@ma...> writes:
>
>> A simulator will not usually perform this type of optimisation. For Verilog in
>> particular, the VPI routines give the user a backdoor mechanism to probe any
>> signals in the design, so it is not generally safe to do so.
>
> Probing is an obstacle for eliminating outputs, but as far as I see,
> it's no fundamental obstacle for constant propagation; the verilog
> compiler could compute the constant value for each eliminated signal
> that could possibly be probed.

The VPI routines also allow the user to force values onto signals.

>> Any decent synthesis tool will do this type of optimisation.
>
> Does it infer automatically which outputs are unused? Or is there some
> kind of verilog syntax to tell it? For now, I do this like
>
>     wire [5:0] dummy;
>     ...
>     /* Final 11-bit add */
>     add_bk16 add ({e0[15:8], 1'b0, e0[6:5], 5'b0},
> 		 {1'b0, e1[14:5], 5'b0}, 1'b0,
> 		 {dummy[5], p[15:5], dummy[4:0]});

A good synthesis tool will automatically remove any logic that can't directly 
or indirectly affect the top-level output signals of a design. It will work 
its way back through flip-flops, removing the flip-flops as well.

Note that the iverilog synthesis option is very basic, and, as far as I'm 
aware, does little or no optimisation of this kind.

>> However, if you are using a synthesis tool, you would normally leave
>> it to generate the optimum adder architecture for each adder instance,
>> inferred from the "+" operator.
>
> With some guidelines for the optimization, to say, e.g., if you want an
> adder with low latency or small area?

You normally give a synthesis tool timing constraints (e.g. minimum clock 
period) and it will try to minimise cell area whilst still meeting those 
constraints. If the timing constraints are easy to meet, it will choose a 
low-area architecture (e.g. ripple carry); if they are hard to meet, it will 
choose a more complex architecture.

> I'm looking into adders and multipliers right now, in part because I
> think they're good examples for learning verilog, in part because the
> state-of-the-art seems to be so far ahead of what I was taught in the
> digital electronics courses. And for a pipelined multiplier, it seems
> difficult rely on the '*' operator when one wants to split it into
> multiple stages with registers in between?

The more advanced synthesis tools will move pipeline registers into a logic 
cone. So you can write the Verilog as a multiply operator followed by one or 
more pipeline register stages, and the synthesis tool will create a suitably 
pipelined multiplier.

Martin