Re: [Iverilog-devel] Handling of constant inputs and unused outputs

[<ni...@ly...>]

Martin Whitaker <mai...@ma...> writes:

> A simulator will not usually perform this type of optimisation. For Verilog in 
> particular, the VPI routines give the user a backdoor mechanism to probe any 
> signals in the design, so it is not generally safe to do so.

Probing is an obstacle for eliminating outputs, but as far as I see,
it's no fundamental obstacle for constant propagation; the verilog
compiler could compute the constant value for each eliminated signal
that could possibly be probed.

> Any decent synthesis tool will do this type of optimisation.

Does it infer automatically which outputs are unused? Or is there some
kind of verilog syntax to tell it? For now, I do this like

   wire [5:0] dummy;
   ...
   /* Final 11-bit add */
   add_bk16 add ({e0[15:8], 1'b0, e0[6:5], 5'b0},
		 {1'b0, e1[14:5], 5'b0}, 1'b0,
		 {dummy[5], p[15:5], dummy[4:0]});

> However, if you are using a synthesis tool, you would normally leave
> it to generate the optimum adder architecture for each adder instance,
> inferred from the "+" operator.

With some guidelines for the optimization, to say, e.g., if you want an
adder with low latency or small area?

I'm looking into adders and multipliers right now, in part because I
think they're good examples for learning verilog, in part because the
state-of-the-art seems to be so far ahead of what I was taught in the
digital electronics courses. And for a pipelined multiplier, it seems
difficult rely on the '*' operator when one wants to split it into
multiple stages with registers in between?

And I do use the '+' and '*' operators in my testbench code.

Regards,
/Niels

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