[Iverilog-devel] Handling of constant inputs and unused outputs

[<ni...@ly...>]

Say I have a module implementing a 16-bit adder (using a Brent-Kung
circuit), and in some other module I need an 11-bit adder. Then I can
use the 16-bit adder with some of the low or high inputs hardwired to
zero.

Are the constants propagated when instantiating the module, eliminating
unneeded operations? And when passing *output* parameters to a module,
is it possible to specify that some output wires are unused, and then
eliminate all operations needed only for producing those outputs? For the
example of an adder module, the carry output may be unneeded for some
instances, and then a couple of operations can be eliminated.

Regards,
/Niels

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