Re: [Iverilog-devel] How to get gate count and delay for a (combinatorial) circuit?

[<ni...@ly...>]

Stephen Williams <st...@ic...> writes:

> Humm, the sizer target is only available in the git repository,
> in the master branch:-(

That explains why it didn't work ;-)

I've now checked out and built iverilog from git. Which worked with no
problem. And in the mean time, I also got my 64-bit adder working (based
on the ideas on
http://robey.lag.net/2012/11/14/how-to-add-numbers-2.html). iverilog
-tsizer add-h64.vl ... now says

**** TOTALS
     Flip-Flops   : 0
     Logic Gates  : 724
     MUX[2]: 63 slices

I guess the "MUX" count is from the final carry select logic, with a
couple of lines of the type

   assign c[1] = c[0] ? s1c1[8] : s1c0[8];
   assign c[2] = c[1] ? s2c1[8] : s2c0[8];
   ...
   assign s[15:8]  = c[0] ? s1c1[7:0] : s1c0[7:0];
   assign s[23:16] = c[1] ? s2c1[7:0] : s2c0[7:0];
   ...

Right?

And if anyone would like to have a look at this code (total of 150 lines
divided into 4 modules) and teach me how to do it better (maybe using
generate for repeated blocks like above, or multidimensional arrays
instead of variables like sXc0, X = 1,2,...,7), I'd be most grateful.

Thanks and regards,
/Niels

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