From: Stephen W. <st...@ic...> - 2014-11-09 23:54:00
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-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Humm, the sizer target is only available in the git repository, in the master branch:-( It may be time to make a snapshot. On 11/09/2014 05:20 AM, Niels Möller wrote: > Stephen Williams <st...@ic...> writes: > >> The only accurate gate count fron synthesis is go get the gate >> count from the synthesizer that you are using to targetting your >> device. For FPGAs, that will be the vendor supplied synthesizer. > > I think I'm more interested in a rough gate count for an asic > implementation, than resources used in any particular fpga. > >> That said, you can use the "-tsizer" target to Icarus Verilog to >> get a very (VERY!) rough estimate of gate counts. This is really >> only useful for relative comparisons (i.e. "Did my last change >> cause a lot of new resources to be required?"). > > I think my use will be to (i) get a feeling for the relative > complexity of different parts of a cpu, and (ii) compare different > implementations of the same interface. > > But how do I use this target? I'm trying as follows, > > ~/hack/instr16/hw$ iverilog -tsizer -s add_bk8 add-bk8.vl > add-gp.vl ERROR: Unable to read config file: > /usr/lib/ivl/sizer.conf : error: target_design entry point is > missing. error: Code generator failure: -2 > > add-bk8.vl defines a moule add_bk8, implementing an 8-bit > Brent-Kung adder. Which is my intended "top-level" circuit. > add-gp.vl is a helper module to combine two sets of > generate/propagate signals, instantiated multiple times in > add-bk8.vl. > > And what about gate delay, can I get that for selected > input/output pairs? I guess it's possible to try synthesis using > iverilog or yosys and then do postprocessing of the generated > netlist, but I was hoping for something simpler... > > Regards, /Niels > - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlRf/o4ACgkQrPt1Sc2b3ilnlACfTXpFM0cT2hc9be039GDH/w9p e8YAoIjuYtA3jNlerxQYgXRvUyNKq5Ec =6mUj -----END PGP SIGNATURE----- |