Re: [Iverilog-devel] How to get gate count and delay for a (combinatorial) circuit?

[Martin W. <mai...@ma...>]

For synthesis, I would suggest taking a look at

   http://www.clifford.at/yosys/about.html

Martin

ni...@ly... (Niels Möller) wrote:
> Hi,
>
> I'm trying to learn verilog (with the ultimate goal of eventually
> implementing a cpu of my own design). As a warmup, I'm starting with
> combinatorial circuits for arithmetic, and I've been reading up on
> Wallace trees and Kogge-Stone adders and variants.
>
> I organize this as a module implementing each circuit, and a "testbench"
> which exercises it with some inputs (exhaustive testing for small
> operations). I just realized that I could have the verilog testbench
> also check if the outputs are correct, at least for basic arithmetic.
> And after searching the net for quite a while I also found
> $finish_and_return, which is very handy to signal failures from the
> testbench. Which all seems pretty nice.
>
> For synthesis, I won't attempt real synthesis anytime soon, but it would
> be nice to be able to get some numbers for the gate count for a circuit,
> and the gate delay between inputs and outputs (and any other properties
> that indicate if the implementation makes sense). Initially for
> combinatorial circuits, since that's what I'm playing with. Is there any
> easy way to get that information from iverilog's synthesizer?
>
> Best regards,
> /Niels
>